Easy Notes Of Microprocessor unit-1 @Computer Diploma

Description

1.1 8086 Microprocessor: Salient Features and Pin Descriptions 📌

Salient Features

The 8086 is an enhanced 16-bit microprocessor developed by Intel in 1978.²

• Architecture: It is a 16-bit microprocessor, meaning its ALU, internal registers, and internal data bus are 16 bits wide.³

• Memory Addressing: It has a 20-bit address bus, allowing it to access ⁴$2^{20} = **1\text{ MB}**$ of physical memory locations (from ⁵$00000\text{H}$ to ⁶$FFFFF\text{H}$).⁷

• Data Bus: It has a 16-bit data bus, enabling it to read or write 16 bits (a word) or 8 bits (a byte) at a time.

• I/O Ports: It can address ⁸$2^{16} = **65,536**$ I/O ports.⁹

• Pipelining: It uses a two-stage pipeline (Fetch and Execute) with a 6-byte instruction prefetch queue to speed up instruction execution by overlapping fetch and execution cycles.¹⁰

• Operating Modes: It supports two operating modes:¹¹

  • Minimum Mode: Suitable for single-processor systems.¹²

  • Maximum Mode: Suitable for multiprocessor systems

• Registers: It has fourteen 16-bit registers.

• Clock Speed: It was available in different versions, typically ¹³$5\text{ MHz}$, ¹⁴$8\text{ MHz}$, and ¹⁵$10\text{ MHz}$.¹⁶

Pin Descriptions

The 8086 is a 40-pin Dual In-line Package (DIP).¹⁷ Many pins are multiplexed, meaning they serve dual purposes depending on the timing.¹⁸

Shutterstock

1.2 Architecture of 8086: Functional Block Diagram & Register Organization

The 8086 architecture is logically divided into two independent functional units to achieve parallel processing: the Bus Interface Unit (BIU) and the Execution Unit (EU).¹⁹

Functional Block Diagram

1. Bus Interface Unit (BIU)

   • Purpose: Handles all external bus operations like fetching instructions, reading/writing operands, and generating physical addresses.²⁰

   • Components:

     • Instruction Queue (6-bytes): A FIFO (First-In, First-Out) buffer that stores prefetched instruction bytes, enabling pipelining.²¹

     • Segment Registers (CS, DS, SS, ES): 16-bit registers used for memory segmentation to calculate the 20-bit physical address.²²

     • Instruction Pointer (IP): A 16-bit register that holds the offset address of the next instruction to be fetched from the Code Segment.²³

     • Address Generation Circuit: Combines the segment register content (shifted left by 4 bits) with the offset address to produce the 20-bit physical address.²⁴

2. Execution Unit (EU)

   • Purpose: Decodes and executes instructions received from the BIU’s instruction queue.²⁵

   • Components:

     • Arithmetic and Logic Unit (ALU): Performs 16-bit arithmetic and logic operations.²⁶

     • Control Unit (CU): Decodes instructions and generates control signals.

     • General Purpose Registers (AX, BX, CX, DX):²⁷ Used for data storage and temporary results.²⁸

     • Pointer and Index Registers (SP, BP, SI, DI):²⁹ Used to hold offset addresses for various addressing modes.³⁰

     • Flag Register (PSW): A 16-bit register that stores the status of the result of ALU operations and controls CPU operation.³¹

Register Organization

The 8086 has fourteen 16-bit registers, grouped as follows:

1. General Purpose Registers (Data Registers)

   • AX (Accumulator): Used for I/O operations and arithmetic.³² Can be split into AH (High) and AL (Low) 8-bit registers.³³

   • BX (Base Register): Used as a base register for memory addressing.³⁴ Can be split into BH and BL.³⁵

   • CX (Count Register): Used as a counter for loop and string instructions.³⁶ Can be split into CH and CL.³⁷

   • DX (Data Register): Used for I/O port addressing and in multiplication/division operations. Can be split into DH and DL.³⁸

2. Segment Registers (Used by BIU)³⁹

   • CS (Code Segment): Stores the base address of the memory segment containing the program instructions.⁴⁰

   • DS (Data Segment): Stores the base address of the memory segment containing program data.⁴¹

   • SS (Stack Segment):⁴² Stores the base address of the memory segment containing the stack.⁴³

   • ES (Extra Segment): Stores the base address of an extra data segment (often used for string operations).

3. Pointer and Index Registers (Used by EU)

   • IP (Instruction Pointer): Holds the offset address of the next instruction in the Code Segment.⁴⁵ (Used with CS)

   • SP (Stack Pointer):⁴⁶ Holds the offset address of the top of the stack in the Stack Segment. (Used with SS)

   • BP (Base Pointer):⁴⁷ Holds the offset address of a data item in the Stack Segment, primarily for accessing function parameters.⁴⁸ (Used with SS)

   • SI (Source Index): Holds the offset address of the source data in the Data Segment for string operations.⁴⁹ (Used with DS)

   • DI (Destination Index): Holds the offset address of the destination data in the Extra Segment for string operations.⁵⁰ (Used with ES)

4. Flag Register (Status Register)

   • A 16-bit register where only 9 bits are actively used.⁵¹ It contains Status Flags (CF, PF, AF, ZF, SF, OF) and Control Flags (TF, IF, DF).

1.3 Concept of Pipelining

Pipelining is a technique used in the 8086 to increase the speed of execution (throughput) by overlapping the instruction fetch cycle with the instruction execution cycle.⁵²

• Two Independent Units: The 8086 architecture enables pipelining by separating the processor into the Bus Interface Unit (BIU) and the Execution Unit (EU), allowing them to operate in parallel (asynchronously).⁵³

• BIU Task (Fetch): The BIU fetches up to 6 bytes of the next sequential instructions from memory and stores them in its Instruction Queue whenever the bus is free and the queue has at least two empty spaces.⁵⁴

• EU Task (Execute): The EU reads the instruction bytes from the instruction queue, decodes them, and executes them.⁵⁵

• Parallel Operation: While the EU is executing the current instruction, the BIU is simultaneously fetching the next instructions.⁵⁶ This reduces the time the EU has to wait for instructions to arrive from memory, thus improving overall performance.

• Pipeline Flush: If a branch or jump instruction is executed, the instructions already loaded in the queue are no longer the next sequential instructions and become irrelevant.⁵⁷ In this case, the queue is flushed (cleared), and the BIU begins fetching from the new target address, causing a temporary performance drop.⁵⁸

1.4 Memory Segmentation and Physical Memory Address Generation

Memory Segmentation

The 8086 uses memory segmentation to achieve its ⁵⁹$1\text{ MB}$ memory addressing capability with only 16-bit registers.⁶⁰

• Logical Division: The ⁶¹$1\text{ MB}$ of physical memory is logically divided into smaller, independent units called segments.⁶²

• Segment Size: Each segment can have a maximum size of ⁶³$64\text{ KB}$ (⁶⁴$2^{16}$ bytes), which can be addressed by a 16-bit offset.⁶⁵

• Active Segments: The 8086 works with four primary segments at any given time, whose starting addresses are held in the four 16-bit Segment Registers (CS, DS, SS, ES).⁶⁶

• Advantage: It allows for flexible memory management, code/data/stack separation, and allows the 16-bit registers to address the 20-bit address space.⁶⁷

Physical Memory Address Generation

The CPU generates a 20-bit Physical Address (PA) from a 32-bit Logical Address (a combination of a 16-bit Segment Address and a 16-bit Offset Address, written as Segment:Offset).⁶⁸

The BIU’s address generation circuit calculates the 20-bit Physical Address using the following formula:

Equivalently, multiplying by 16 is the same as shifting the 16-bit segment address left by 4 bits and padding with four $0$‘s.

Example:

• Segment Address (CS): $1000\text{H}$

• Offset Address (IP): $2535\text{H}$

1. Shift Segment Address left by 4 bits (add a trailing $0\text{H}$):
   $$1000\text{H} \rightarrow 10000\text{H}$$
2. Add the Offset Address:
   $$\begin{array}{r} 10000\text{H} \\ + \ 2535\text{H} \\ \hline 12535\text{H} \end{array}$$

• Physical Address (PA): ⁶⁹$12535\text{H}$ (a 20-bit address)⁷⁰

• This mechanism is why the starting address of any segment must be divisible by 16 (i.e., a paragraph boundary).⁷¹